1. Field of the Invention
The present invention relates to an inter-laminar film adhesive for multi-layer printed wiring boards, capable of integrally carrying out the coating process of an inner-layer circuit pattern and the filling process of a resin in a superficial via hole and/or a through-hole simultaneously on a multi-layer printed wiring board of a build-up type where a conductive layer and an insulation layer are alternatively built up; and a process for producing a multilayer printed wiring board using the same.
2. Discussion of the Background
Conventional processes for producing a multi-layer printed wiring board generally comprise lamination pressing through several prepreg sheets produced by impregnating an insulation adhesive layer glass cloth impregnated with an epoxy resin to prepare the cloth at B stage and obtaining inter-laminar communication by way of through-holes. However, the process is costly and conducts heating and molding under pressure through lamination pressing, thus requiring large equipment and a long processing time. Additionally the process requires the use of glass cloth with a relatively high dielectric constant as the prepreg sheet, which limits the ability to reduce the inter-laminar thickness. The process is also problematic because of the insulation concern due to CAF.
As one way to overcome such problems, attention has recently been focused on buildup production technique of multi-layer printed wiring boards, comprising alternately laminating an organic insulation layer on the conductor layer of an internal-layer circuit board. Japanese Patent Laid-open No. 7-202426 and 8-157566 disclose a method for producing a multi-layer printed wiring board, comprising coating and preliminarily drying an underlining adhesive on an internal-layer circuit board with a circuit formed therein and bonding a copper foil or a copper foil with an adhesive on the board.
Additionally, in Japanese Patent Laid-open No. 8-64960, a method is disclosed for producing a multi-layer printed wiring board, comprising coating and preliminary drying of an underlining adhesive and attachment of a film additive adhesive followed by curing under heating, scrubbing with an alkaline oxidant, and plating to form a conductor layer. Because the underlining adhesive layer is formed in an ink form by these methods, however, the possibility of dust contamination into the adhesive layer during the processes is high, which causes circuit failure due to disconnection and short circuiting.
As a method with no use of an underlining adhesive, Japanese Patent Laid-open No. 7-202418 discloses a method for producing a multi-layer printed wiring board, by forming an adhesive layer, comprising a high molecular epoxy resin and an epoxy resin, as liquids on a copper foil, and attaching the resulting copper foil with the adhesive onto an internal-layer circuit board. This method is problematic, however, in that the copper foil with the adhesive is readily wrinkled or damaged during lamination. Additionally, any of the above-noted methods has two major drawbacks from the respect of workability and characteristic properties of the final product, in that (1) these methods require a hole filling process, by means of a hole filling resin and the like, if through-holes are present on an internal-layer circuit board and (2) voids readily develop in superficial via holes if they are present.